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| ltm9012 1 9012f typical a pplica t ion fea t ures descrip t ion quad 14-bit, 125msps adc with integrated drivers the ltm ? 9012 is a 4-channel, simultaneous sampling 14-bit module ? analog-to-digital converter (adc) with integrated, fixed gain, differential adc drivers. the low noise amplifiers are suitable for single-ended drive and pulse train signals such as imaging applications. each channel includes a lowpass filter between the driver out- put and adc input. dc specs include 1.2lsb inl (typ), 0.3lsb dnl (typ) and no missing codes over temperature. the transition noise is a low 1.2lsb rms . the digital outputs are serial lvds and each channel out - puts two bits at a time (2-lane mode). at lower sampling rates there is a one bit option (1-lane mode). the lvds drivers have optional internal termination and adjustable output levels to ensure clean signal integrity. the enc + and enc C inputs may be driven differentially or single-ended with a sine wave, pecl, lvds, ttl or cmos inputs. an internal clock duty cycle stabilizer al- lows high performance at full speed for a wide range of clock duty cycles. single-ended sensor digitization a pplica t ions n 4-channel simultaneous sampling adc with integrated, fixed gain, differential drivers n 68.3db snr n 78db sfdr n low power: 1.27w total, 318mw per channel n 1.8v adc core and 3.3v analog input supply n serial lvds outputs: 1 or 2 bits per channel n shutdown and nap modes n 11.25mm 15mm bga package n industrial imaging n medical imaging n multichannel data acquisition n nondestructive testing l , lt, ltc, ltm, linear technology, the linear logo and module are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. ltm9012, 125msps, 70mhz fft 9012 ta01a ltm9012 14 fpga pipeline adc 14 pipeline adc 14 pipeline adc image sensor 14 pipeline adc internal reference & supply bypass capacitors pll sck enc + enc ? sdi sdo par/ ser cs encode clock channel 1 channel 2 channel 3 channel 4 fr + fr ? dco + dco ? data serializer encoder and lvds drivers 1.8v ov dd 1.8v v dd 3.3v ? ? ? v cc v ref frequency (mhz) 0 amplitude (dbfs) ?90 ?80 0 ?10 25155 45 9012 ta01b ?100 ?110 ?120 ?30 ?20 ?40 ?50 ?60 ?70 35 55 302010 50 40 60
ltm9012 2 9012f p in c on f igura t ion a bsolu t e maxi m u m r a t ings supply voltages v dd , ov dd ................................................ C0 .3v to 2v v cc ........................................................ C0.3v to 5.5v analog input voltage (ch n + , ch n C , shdn n ) (note 3) ....................................................... C 0.3v to v cc analog input voltage (par/ ser , sense) (note 4) ........................................ C 0.3v to (v dd + 0.2v) digital input voltage (enc + , enc C , cs , sdi, sck) (note 5) ..................................................... C 0.3v to 3.9v sdo (note 5) ............................................. C0.3v to 3.9v digital output voltage ................ C 0.3v to (ov dd + 0.3v) operating temperature range ltm9012c ............................................... 0 c to 70c ltm9012i ............................................. C40c to 85c storage temperature range .................. C 65c to 150c (notes 1, 2) bga package 221-lead (15mm 11.25mm) top view s r q p n m l k j h g f e d c b a 1 2 3 4 5 6 13121110987 ch4 + shdn3 shdn2 ch4 ? ch3 + ch3 ? ch2 + ch2 ? ch1 + ch1 ? v cc2 v cc1 v cc4 v cc3 shdn4 shdn1 enc + v dd sense v dd sdo d1a ? d1a + d4b ? d4b + d4a ? d4a + d3b ? d3b + d2a ? d2a + d3a ? d3a + fr ? fr + par/ ser enc ? sdi cs sck ref d1b ? d1b + all else = gnd ov dd dco ? dco + d2b ? d2b + t jmax = 125c, ja = 16.5c/w, jctop = 15c/w, jcbottom = 6.3c/w, jboard = 10.4c/w values determined per jesd 51-9 weight = 1.07g o r d er i n f or m a t ion lead free finish tray part marking* package description temperature range ltm9012cy-ab#pbf ltm9012cy-ab#pbf ltm9012yab 221-lead (15mm 11.25mm) plastic bga 0c to 70c ltm9012iy-ab#pbf ltm9012iy-ab#pbf ltm9012yab 221-lead (15mm 11.25mm) plastic bga C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ ltm9012 3 9012f c onver t er c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 6) parameter conditions min typ max units resolution (no missing codes) l 14 bits integral linearity error differential analog input (note 7) l C5 1.2 5 lsb differential linearity error differential analog input l C0.9 0.3 0.9 lsb offset error (note 8) l C37 3 37 mv gain error internal reference external reference l C3.6 C1.3 C1.3 3.0 %fs %fs offset drift 20 v/c full-scale drift internal reference external reference 35 25 ppm/c ppm/c gain matching external reference 0.2 %fs offset matching 3 mv transition noise external reference 1.2 lsb rms a nalog i npu t the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 6) symbol parameter conditions min typ max units v in differential analog input range (ch + C ch C ) at C1dbfs ltm9012-ab l 0.2 v p-p v in(cm) analog input common mode (ch + + ch C )/2 differential analog input (note 9) 0 to 1.5 v v sense external voltage reference applied to sense external reference mode l 0.625 1.250 1.300 v r in differential input resistance ltm9012-ab 100 i in(p/s) input leakage current 0 < par/ ser < v dd l C3 3 a i in(sense) input leakage current 0.625v < sense < 1.3v l C6 6 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay jitter 0.15 ps rms cmrr analog input common mode rejection ratio 90 db bw-3db 3db corner of internal lowpass filter 90 mhz dyna m ic a ccuracy the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 6) symbol parameter conditions min typ max units snr signal-to-noise ratio 70mhz input l 66.5 68.3 dbfs sfdr spurious free dynamic range 2nd or 3rd harmonic 70mhz input l 66.9 78 dbfs spurious free dynamic range 4th harmonic or higher 70mhz input l 76.9 86 dbfs s/n+d signal-to-noise plus distortion ratio 70mhz input l 64.7 66.7 dbfs crosstalk, near channel 10mhz (note 12) 70 dbc crosstalk, far channel 10mhz (note 12) 90 dbc ltm9012 4 9012f i n t ernal r e f erence c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. parameter conditions min typ max units v ref output voltage i out = 0 1.225 1.250 1.275 v v ref output temperature drift 25 ppm/c v ref output resistance C400a < i out < 1ma 7 v ref line regulation 1.7v < v dd < 1.9v 0.6 mv/v digi t al i npu t s an d o u t pu t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 6) symbol parameter conditions min typ max units encode inputs (enc + , enc C ) differential encode mode (enc C not tied to gnd) v id differential input voltage (note 9) l 0.2 v v icm common mode input voltage internally set externally set (note 9) l 1.1 1.2 1.6 v v v in input voltage range enc + , enc C to gnd l 0.2 3.6 v r in input resistance (see figure 3) 10 k c in input capacitance 3.5 pf single-ended encode mode (enc C tied to gnd) v ih high level input voltage v dd = 1.8v 1.26 v v il low level input voltage v dd = 1.8v 0.54 v v in input voltage range enc + to gnd 0 to 3.6 v r in input resistance (see figure 4) 30 k c in input capacitance 3.5 pf digital inputs (cs, sdi, sck in serial or parallel programming mode. sdo in parallel programming mode) v ih high level input voltage v dd = 1.8v l 1.3 v v il low level input voltage v dd = 1.8v l 0.6 v i in input current v in = 0v to 3.6v l C10 10 a c in input capacitance 3 pf sdo output (serial programming mode. open-drain output. requires 2k pull-up resistor if sdo is used) r oh logic low output resistance to gnd v dd = 1.8v, sdo = 0v 200 i oh logic high output leakage current sdo = 0v to 3.6v l C10 10 a c out output capacitance 3 pf digital input (shdn) v ih high level input voltage v cc = 3.3v l 0.97 1.4 v v il low level input voltage v cc = 3.3v l 0.6 0.95 v r shdn shdn pull-up resistor v shdn = 0v to 0.5v l 90 150 210 k digital data outputs v od differential output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 247 125 350 175 454 250 mv mv v os common mode output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 1.125 1.125 1.250 1.250 1.375 1.375 v v r term on-chip termination resistance termination enabled, ov dd = 1.8v 100 ltm9012 5 9012f p ower r equire m en t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 6) symbol parameter conditions min typ max units v dd adc supply voltage (note 10) l 1.7 1.8 1.9 v ov dd adc output supply voltage (note 10) l 1.7 1.8 1.9 v v cc amplifier supply voltage (note 10) l 2.7 3.3 3.6 v i vdd adc supply current sine wave input l 298 320 ma i ovdd adc output supply current 2-lane mode, 1.75ma mode 2-lane mode, 3.5ma mode l l 27 49 31 54 ma ma i vcc amplifier supply current l 208 224 ma p diss 2-lane mode, 1.75ma mode 2-lane mode, 3.5ma mode l l 1271 1311 1473 1517 mw mw p sleep 3 mw p nap 85 mw p diffclk power decrease with single-ended encode mode enabled 20 mw ti m ing c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 6) symbol parameter conditions min typ max units f s sampling frequency (note 10, note 11) l 5 125 mhz t encl enc low time (note 9) duty cycle stabilizer off duty cycle stabilizer on l l 3.8 2 4 4 100 100 ns ns t ench enc high time (note 9) duty cycle stabilizer off duty cycle stabilizer on l l 3.8 2 4 4 100 100 ns ns t ap sample-and-hold acquisition delay time 0 ns digital data outputs (r term = 100 differential, c l = 2pf to gnd on each output) t ser serial data bit period 2-lanes, 16-bit serialization 2-lanes, 14-bit serialization 2-lanes, 12-bit serialization 1-lane, 16-bit serialization 1-lane, 14-bit serialization 1-lane, 12-bit serialization 1/(8 ? f s ) 1/(7? f s ) 1/(6? f s ) 1/(16? f s ) 1/(14? f s ) 1/(12? f s ) sec sec sec sec sec sec t frame fr to dco delay (note 9) l 0.35 ? t ser 0.5 ? t ser 0.65 ? t ser sec t data data to dco delay (note 9) l 0.35 ? t ser 0.5 ? t ser 0.65 ? t ser sec t pd propagation delay (note 9) l 0.7n + 2 ? t ser 1.1n + 2 ? t ser 1.5n + 2 ? t ser sec t r output rise time data, dco, fr, 20% to 80% 0.17 ns t f output fall time data, dco, fr, 20% to 80% 0.17 ns dco cycle-cycle jitter t ser = 1ns 60 ps p-p pipeline latency 6 cycles spi port timing (note 9) t sck sck period write mode read back mode, c sdo = 20pf, r pullup = 2k l l 40 250 ns ns t s cs to sck setup time l 5 ns t h sck to cs setup time l 5 ns t ds sdi setup time l 5 ns t dh sdi hold time l 5 ns t do sck falling to sdo valid read back mode, c sdo = 20pf, r pullup = 2k l 125 ns ltm9012 6 9012f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd (unless otherwise noted). note 3: input pins are protected by steering diodes to either supply. if the inputs should exceed either supply voltage, the input current should be limited to less than 10ma. in addition, the inputs chn + , chn C are protected by a pair of back-to-back diodes. if the differential input voltage exceeds 1.4v, the input current should be limited to less than 10ma. note 4: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents greater than 100ma below gnd or above v dd without latchup. note 5: when these pin voltages are taken below gnd they will be clamped by internal diodes. when these pin voltages are taken above v dd they will not be clamped by internal diodes. this product can handle input currents greater than 100ma below gnd without latchup. e lec t rical c harac t eris t ics note 6: v cc = 3.3v, v dd = ov dd = 1.8v, f sample = 125mhz, 2-lane output mode, differential enc + /enc C = 2v p-p sine wave, input range = 200mv p-p with differential drive, unless otherwise noted. note 7: integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 8: offset error is the offset voltage measured from C0.5 lsb when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2s complement output mode. note 9: guaranteed by design, not subject to test. note 10: recommended operating conditions. note 11: the maximum sampling frequency depends on the speed grade of the part and also which serialization mode is used. the maximum serial data rate is 1000mbps so t ser must be greater than or equal to 1ns. note 12: near-channel crosstalk refers to ch1 and ch2. far channel crosstalk refers to ch1 to ch4. ti m ing diagra m s analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t ser t ser t pd t data t frame sample n-6 *see the digital outputs section sample n-5 sample n-4 n+1 n 9012 td01 d5 d3 d1 0 d13 d11 d9 d7 d5 d3 d1 0 d13 d11 d9 out#a ? out#a + fr ? fr + d4 d2 d0 0 d12 d10 d8 d6 d4 d2 d0 0 d12 d10 d8 out#b ? out#b + 2-lane output mode, 16-bit serialization* ltm9012 7 9012f ti m ing diagra m s 2-lane output mode, 14-bit serialization analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t ser t ser t pd t data t frame sample n-6 sample n-5 sample n-4 sample n-3 n+1 n+2 n 9012 td02 d7 d5 d3 d1 d13 d11 d9 d7 d5 d3 d1 d13 d11 d9 d7 d5 d3 d1 d13 d11 d9 out#a ? out#a + fr ? fr + d6 d4 d2 d0 d12 d10 d8 d6 d4 d2 d0 d12 d10 d8 d6 d4 d2 d0 d12 d10 d8 out#b ? out#b + note that in this mode fr + /fr ? has two times the period of enc + /enc ? 2-lane output mode, 12-bit serialization analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t ser t ser t pd t data t frame sample n-6 sample n-5 sample n-4 n+1 n 9012 td03 d9 d7 d5 d3 d13 d11 d9 d7 d5 d3 d13 d11 d9 out#a ? out#a + fr + fr ? d8 d6 d4 d2 d12 d10 d8 d6 d4 d2 d12 d10 d8 out#b ? out#b + ltm9012 8 9012f ti m ing diagra m s 1-lane output mode, 16-bit serialization analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t pd t data t frame sample n-6 sample n-5 sample n-4 n+1 n t ser t ser 9012 td04 d1 d0 0 0 d13 d12 d11 d10 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 d13 out#a ? out#a + fr ? fr + out#b + , out#b ? are disabled 1-lane output mode, 14-bit serialization analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t pd t data t frame sample n-6 sample n-5 sample n-4 n+1 n t ser t ser 9012 td05 d3 d2 d1 d0 d13 d12 d11 d10 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d13 out#a ? out#a + fr ? fr + out#b + , out#b ? are disabled ltm9012 9 9012f ti m ing diagra m s 1-lane output mode, 12-bit serialization analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t pd t data t frame sample n-6 sample n-5 sample n-4 n+1 n t ser t ser 9012 td06 d5 d4 d3 d2 d13 d12 d11 d10 d12 d11 d9 d8 d7 d6 d5 d4 d3 d2 d13 out#a ? out#a + fr ? fr + out#b + , out#b ? are disabled a6 t s t ds a5 a4 a3 a2 a1 a0 xx d7 d6 d5 d4 d3 d2 d1 d0 xx xx xx xx xx xx xx cs sck sdi r/w sdo high impedance spi port timing (readback mode) spi port timing (write mode) t dh t do t sck t h a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 9012 td07 cs sck sdi r/w sdo high impedance ltm9012 10 9012f typical p er f or m ance c harac t eris t ics 64k point 2-tone fft, f in = 4.8mhz and f in = 5.2mhz, C7dbfs per tone, sense = v dd 64k point 2-tone fft, f in = 70mhz and f in = 75mhz, C7dbfs per tone, sense = v dd differential non-linearity (dnl) vs output code integral non-linearity (inl) vs output code pulse response frequency response i ovdd vs sample rate, 5mhz sine wave input C1dbfs 64k point fft, f in = 5mhz, C1dbfs, sense = v dd 64k point fft, f in = 70mhz, C1dbfs, sense = v dd sample rate (msps) 0 i ovdd (ma) 30 40 60 50 25 75 125 9012 g01 20 10 0 50 100 1-lane 1.75ma 1-lane 3.5ma 2-lane 1.75ma 2-lane 3.5ma output code 0 dnl error (lsb) ?0.4 ?0.3 0.5 0.4 4096 12288 16384 9012 g06 ?0.5 0.2 0.3 0.1 0 ?0.1 ?0.2 8192 output code 0 inl error (lsb) ?1.5 2.0 1.5 4096 12288 16384 9012 g07 ?2.0 0.5 1.0 0 ?0.5 ?1.0 8192 time (s) 0 2000 16000 14000 0.1 0.9 1 9012 g08 0 10000 12000 8000 6000 4000 0.80.70.60.50.40.30.2 baseband frequency (mhz) dbfs 1 ?35 0 ?5 10 1000 100 9012 g09 ?40 ?15 ?10 ?20 ?25 ?30 frequency (mhz) 0 amplitude (dbfs) ?90 ?80 0 ?10 25155 45 9012 g02 ?100 ?110 ?120 ?30 ?20 ?40 ?50 ?60 ?70 35 55 302010 50 40 60 frequency (mhz) 0 amplitude (dbfs) ?90 ?80 0 ?10 25155 45 9012 g03 ?100 ?110 ?120 ?30 ?20 ?40 ?50 ?60 ?70 35 55 302010 50 40 60 frequency (mhz) 0 amplitude (dbfs) ?90 ?80 0 ?10 25155 45 9012 g04 ?100 ?110 ?120 ?30 ?20 ?40 ?50 ?60 ?70 35 55 302010 50 40 60 frequency (mhz) 0 amplitude (dbfs) ?90 ?80 0 ?10 25155 45 9012 g05 ?100 ?110 ?120 ?30 ?20 ?40 ?50 ?60 ?70 35 55 302010 50 40 60 ltm9012 11 9012f p in func t ions v cc1 (h10, h13): channel 1 amplifier supply. v cc is internally bypassed to ground with 0.1f in parallel with 0.01f ceramic capacitors, additional bypass capacitance is optional. the recommended operating voltage is 3.3v. v cc2 (c8, c12): channel 2 amplifier supply. v cc is in- ternally bypassed to ground with 0.1f in parallel with 0.01f ceramic capacitors, additional bypass capacitance is optional. the recommended operating voltage is 3.3v. v cc3 (c2, c6): channel 3 amplifier supply. v cc is in- ternally bypassed to ground with 0.1f in parallel with 0.01f ceramic capacitors, additional bypass capacitance is optional. the recommended operating voltage is 3.3v. v cc4 (h1, h4): channel 4 amplifier supply. v cc is in- ternally bypassed to ground with 0.1f in parallel with 0.01f ceramic capacitors, additional bypass capacitance is optional. the recommended operating voltage is 3.3v. v dd (n4, n5, n9, n10): adc analog supply. v dd is inter - nally bypassed to ground with 0.1f ceramic capacitors, additional bypass capacitance is optional. the recom- mended operating voltage is 1.8v. ov dd (r7, r8, s8): adc digital output supply. ov dd is internally bypassed to ground with 0.1f ceramic ca - pacitors, additional bypass capacitance is optional. the recommended operating voltage is 1.8v. gnd: ground. use multiple vias close to pins. ch1 + (a11): channel 1 noninverting analog input. ch1 C (a12): channel 1 inverting analog input. ch2 + (a8): channel 2 noninverting analog input. ch2 C (a9): channel 2 inverting analog input. ch3 + (a5): channel 3 noninverting analog input. ch3 C (a6): channel 3 inverting analog input. ch4 + (a2): channel 4 noninverting analog input. ch4 C (a3): channel 4 inverting analog input. shdn1 (g11): channel 1 amplifier shutdown. connect- ing shdn1 to v cc or floating results in normal (active) operating mode. connecting shdn1 to gnd results in a low power shutdown state on amplifier 1. shdn2 (d9): channel 2 amplifier shutdown. connect- ing shdn2 to v cc or floating results in normal (active) operating mode. connecting shdn2 to gnd results in a low power shutdown state on amplifier 2. shdn3 (d3): channel 3 amplifier shutdown. connect- ing shdn3 to v cc or floating results in normal (active) operating mode. connecting shdn3 to gnd results in a low power shutdown state on amplifier 3. shdn4 (g1): channel 4 amplifier shutdown. connect- ing shdn4 to v cc or floating results in normal (active) operating mode. connecting shdn4 to gnd results in a low power shutdown state on amplifier 4. enc + (n1): encode input. conversion starts on the rising edge. enc C (p1): encode complement input. conversion starts on the falling edge. cs (p4): in serial programming mode, (par/ser = 0v), cs is the serial interface chip select input. when cs is low, sck is enabled for shifting data on sdi into the mode control registers. in the parallel programming mode (par/ ser = v dd ), cs selects 2-lane or 1-lane output mode. cs can be driven with 1.8v to 3.3v logic. sck (p5): in serial programming mode, (par/ser = 0v), sck is the serial interface clock input. in the parallel programming mode (par/ ser = v dd ), sck selects 3.5ma or 1.75ma lvds output currents. sck can be driven with 1.8v to 3.3v logic. sdi (p3): in serial programming mode, (par/ser = 0v), sdi is the serial interface data input. data on sdi is clocked into the mode control registers on the rising edge of sck. in the parallel programming mode (par/ ser = v dd ), sdi can be used to power down the part. sdi can be driven with 1.8v to 3.3v logic. sdo (p9): in serial programming mode, (par/ser = 0v), sdo is the optional serial interface data output. data on sdo is read back from the mode control registers and can be latched on the falling edge of sck. sdo is an open- drain nmos output that requires an external 2k pull-up resistor to 1.8v C 3.3v. if read back from the mode control registers is not needed, the pull-up resistor is not neces- sary and sdo can be left unconnected. in the parallel programming mode (par/ ser = v dd ), sdo is an input that enables internal 100 termination resistors. when used as an input, sdo can be driven with 1.8v to 3.3v logic through a 1k series resistor. ltm9012 12 9012f p in func t ions par/ ser (p10): programming mode selection pin. con- nect to ground to enable the serial programming mode. cs, sck, sdi and sdo become a serial interface that controls the a/d operating modes. connect to v dd to enable the parallel programming mode where cs, sck, sdi and sdo become parallel logic inputs that control a reduced set of the a/d operating modes. par/ ser should be connected directly to ground or the v dd of the part and not be driven by a logic signal. v ref (p11): reference voltage output. v ref is internally bypassed to ground with a 2.2f ceramic capacitor, nomi - nally 1.25v. sense (n11): reference programming pin. connecting sense to v dd selects the internal reference and a 0.1v input range. connecting sense to ground selects the internal reference and a 0.05v input range. an external reference between 0.625v and 1.3v applied to sense selects an input range of 0.08 ? v sense . sense is inter - nally bypassed to ground with a 0.1f ceramic capacitor. lvds outputs all pins in this section are differential lvds outputs. the output current level is programmable. there is an optional internal 100 termination resistor between the pins of each lvds output pair. out1a C /out1a + , out1b C /out1b + (q9/q10, r11/r12): serial data outputs for channel 1. in 1-lane output mode only out1a C /out1a + are used. out2a C /out2a + , out2b C /out2b + (r9/r10, s11/s12): serial data outputs for channel 2. in 1-lane output mode only out2a C /out2a + are used. out3a C /out3a + , out3b C /out3b + (s2/s3, r4/r5): se- rial data outputs for channel 3. in 1-lane output mode only out3a C /out3a + are used. out4a C /out4a + , out4b C /out4b + (r2/r3, q4/q5): se- rial data outputs for channel 4. in 1-lane output mode only out4a C /out4a + are used. fr C /fr + (s4/s5): frame start output. dco C /dco + (s9/s10): data clock output. 1 2 3 4 5 6 7 8 9 10 11 12 13 a gnd ch4 + ch4 C gnd ch3 + ch3 C gnd ch2 + ch2 C gnd ch1 + ch1 C gnd b gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd c gnd v cc3 gnd gnd gnd v cc3 gnd v cc2 gnd gnd gnd v cc2 gnd d gnd gnd shdn3 gnd gnd gnd gnd gnd shdn2 gnd gnd gnd gnd e gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd f gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd g shdn4 gnd gnd gnd gnd gnd gnd gnd gnd gnd shdn1 gnd gnd h v cc4 gnd gnd v cc4 gnd gnd gnd gnd gnd v cc1 gnd gnd v cc1 j gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd k gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd l gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd m gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd n enc + gnd gnd v dd v dd gnd gnd gnd v dd v dd sense gnd gnd p encC gnd sdi cs sck gnd gnd gnd sdo par/ ser ref gnd gnd q gnd gnd gnd d4b C d4b + gnd gnd gnd d1a C d1a + gnd gnd gnd r gnd d4a C d4a + d3b C d3b + gnd ovdd ovdd d2a C d2a + d1b C d1b + gnd s gnd d3a C d3a + fr C fr + gnd gnd ovdd dco C dco + d2b C d2b + gnd p in c on f igura t ion table ltm9012 13 9012f b lock diagra m 9012 bd ltm9012 14-bit adc core ch 1 analog input shdn1 ch 4 analog input ch 3 analog input ch 2 analog input 14-bit adc core v dd/2 out1a + out1a ? out1b + out1b ? out2a + out2a ? out2b + out2b ? out3a + out3a ? out3b + out3b ? out4a + out4a ? out4b + out4b ? sdo sdi sck cs par/ ser dco fr data serializer mode control registers pll enc + enc ? v ref 1.25v reference range select 14-bit adc core 14-bit adc core 1.8v ov dd 1.8v v dd 3.3v v cc diff. ref. amp. ref buffer sense gnd refh refl shdn2 shdn3 v dd/2 shdn4 figure 1. block diagram ltm9012 14 9012f a pplica t ions i n f or m a t ion c onverter o peration the ltm9012 is a low power , 4-channel, 14-bit, 125msps a/d converter that is powered by a 1.8v adc supply and 3.3v driver supplies. each input includes a fixed gain, differential amplifier. the analog inputs can be driven dif - ferentially or single-ended. the encode input can be driven differentially for optimal jitter performance, or single-ended for lower power consumption. the digital outputs are serial lvds to minimize the number of data lines. each channel outputs two bits at a time (2-lane mode). at lower sampling rates there is a one bit per channel option (1-lane mode). many additional features can be chosen by programming the mode control registers through a serial spi port. analog inputs the analog inputs for each channel of the ltm9012 con - sist of a differential amplifier with fixed gain followed by a lowpass filter. the 10x gain version has 49.9 series resistance in each input. the differential input can support single-ended operation by connecting the inverting input to a fixed dc voltage or ground. however, if ground is used, there will be a 6db loss of dynamic range. for maximum dynamic range, con- nect the inverting inputs of the ltm9012 to a dc voltage equal to the median of the voltage excursions of the non- inverting input. an op amp provides an excellent means of providing a low impedance voltage source capable of sourcing and sinking small amounts of current. note the value of this dc voltage should fall between the limits of allowable input common mode voltages. see figure 2 for an example. ltm9012 (1 channel shown) 9012 f02 + ? + ? r f ? ltc6254 v ref signal 0.1f set v ref equal to the dc median of the signal voltage figure 2. single-ended operation the gain of the ltm9012 may also be decreased from the nominal value by adding resistance in series with the signal inputs. the internal op amps are fed by 49.9 series resistors and employ 511 feedback resistors. the voltage gain of the stage is set by the ratio of the feedback resistance to the total series resistance. unity gain, for example, can be realized by adding a 464 resistor in series with each input. reference the ltm9012 has an internal 1.25v voltage reference. for a 2v input range using the internal reference with a unity gain internal amplifier configuration, connect sense to v dd . for a 1v input range using the internal reference, connect sense to ground. for a 2v input range with an external reference, apply a 1.25v reference voltage to sense. the input range can be adjusted by applying a voltage to sense that is between 0.625v and 1.30v. the input range will then be 1.6 ? v sense . the reference is shared by all four adc channels, so it is not possible to independently adjust the input range of individual channels. ltm9012 15 9012f a pplica t ions i n f or m a t ion figure 5. sinusoidal encode drive figure 6. pecl or lvds encode drive encode input the signal quality of the encode inputs strongly affects the a/d noise performance. the encode inputs should be treated as analog signalsdo not route them next to digital traces on the circuit board. there are two modes of opera - tion for the encode inputs: the differential encode mode (figure 3), and the single-ended encode mode (figure 4). the differential encode mode is recommended for sinusoi- dal, pecl, or lvds encode inputs (figure 5 and figure 6). the encode inputs are internally biased to 1.2v through 10k equivalent resistance. the encode inputs can be taken figure 3. equivalent encode input circuit for differential encode mode figure 4. equivalent encode input circuit for single-ended encode mode v dd ltm9012 9012 f03 enc ? enc + 15k v dd differential comparator 30k 30k enc + enc ? 9012 f04 0v 1.8v to 3.3v ltm9012 cmos logic buffer 50 100 0.1f 0.1f 0.1f t1 t1 = ma/com etc1-1-13 resistors and capacitors are 0402 package size 50 ltm9012 9012 f05 enc ? enc + enc + enc ? pecl or lvds clock 0.1f 0.1f 9012 f06 ltm9012 above v dd (up to 3.6v), and the common mode range is from 1.1v to 1.6v. in the differential encode mode, enc C should stay at least 200mv above ground to avoid falsely triggering the single-ended encode mode. for good jitter performance enc + should have fast rise and fall times. the single-ended encode mode should be used with cmos encode inputs. to select this mode, enc C is connected to ground and enc + is driven with a square wave encode input. enc + can be taken above v dd (up to 3.6v) so 1.8v to 3.3v cmos logic levels can be used. the enc + threshold is 0.9v. for good jitter performance enc + should have fast rise and fall times. ltm9012 16 9012f table 1. maximum sampling frequency for all serialization modes. the sampling frequency for potential slower speed grades cannot exceed f sample(max) . serialization mode maximum sampling frequency, f s (mhz) dco frequency fr frequency serial data rate 2-lane 16-bit serialization 125 4 ? f s f s 8 ? f s 2-lane 14-bit serialization 125 3.5 ? f s 0.5 ? f s 7 ? f s 2-lane 12-bit serialization 125 3 ? f s f s 6 ? f s 1-lane 16-bit serialization 62.5 8 ? f s f s 16 ? f s 1-lane 14-bit serialization 71.4 7 ? f s f s 14 ? f s 1-lane 12-bit serialization 83.3 6 ? f s f s 12 ? f s a pplica t ions i n f or m a t ion clock pll and duty cycle stabilizer the encode clock is multiplied by an internal phase-locked loop (pll) to generate the serial digital output data. if the encode signal changes frequency or is turned off, the pll requires 25s to lock onto the input clock. a clock duty cycle stabilizer circuit allows the duty cycle of the applied encode signal to vary from 30% to 70%. in the serial programming mode it is possible to disable the duty cycle stabilizer, but this is not recommended. in the parallel programming mode the duty cycle stabilizer is always enabled. d igit al o utputs the digital outputs of the ltm9012 are serialized l vds signals. each channel outputs two bits at a time (2-lane mode). at lower sampling rates there is a one bit per chan- nel option (1-lane mode). the data can be serialized with 16-, 14-, or 12-bit serialization (see the timing diagrams for details). note that with 12-bit serialization the two lsbs are not availablethis mode is included for compatibility with potential 12-bit versions of these parts. the output data should be latched on the rising and falling edges of the data clock out (dco). a data frame output (fr) can be used to determine when the data from a new conversion result begins. in the 2-lane, 14-bit serialization mode, the frequency of the fr output is halved. the maximum serial data rate for the data outputs is 1gbps, so the maximum sample rate of the adc will depend on the serialization mode as well as the speed grade of the adc (see table 1). the minimum sample rate for all seri - alization modes is 5msps. by default the outputs are standard lvds levels: 3.5ma output current and a 1.25v output common mode volt - age. an external 100 differential termination resistor is required for each lvds output pair. the termination resistors should be located as close as possible to the lvds receiver. the outputs are powered by ov dd which is isolated from the a/d core power. programmable lvds output current the default output driver current is 3.5ma. this current can be adjusted by control register a2 in the serial pro- gramming mode. available current levels are 1.75ma, 2.1ma, 2.5ma, 3ma, 3.5ma, 4ma and 4.5ma. in the parallel programming mode the sck pin can select either 3.5ma or 1.75ma. ltm9012 17 9012f a pplica t ions i n f or m a t ion optional lvds driver internal termination in most cases using just an external 100 termination resistor will give excellent lvds signal integrity. in addi - tion, an optional internal 100 termination resistor can be enabled by serially programming mode control register a2. the internal termination helps absorb any reflections caused by imperfect termination at the receiver. when the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. in the parallel programming mode the sdo pin enables internal termination. internal termination should only be used with 1.75ma, 2.1ma or 2.5ma lvds output current modes. d a ta f orma t table 2 shows the relationship between the analog input voltage and the digital data output bits. by default the output data format is offset binary. the 2s complement format can be selected by serially programming mode control register a1. table 2. output codes vs input voltage chn + to chn C (0.2v range) d13 to d0 (offset binary) d13 to d0 (2s complement) >0.1000000v +0.0999878v +0.0999756v 11 1111 1111 1111 11 1111 1111 1111 11 1111 1111 1110 01 1111 1111 1111 01 1111 1111 1111 01 1111 1111 1110 +0.0000122v +0.0000000v C0.0000122v C0.0000244v 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1111 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1110 C0.0999878v C0.1000000v ltm9012 19 9012f a pplica t ions i n f or m a t ion the sdo pin is an open-drain output that pulls to ground with a 200 impedance. if register data is read back through sdo, an external 2k pull-up resistor is required. if serial data is only written and read back is not needed, then sdo can be left floating and no pull-up resistor is needed. table 4 shows a map of the mode control registers. software reset if serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. the first serial command must be a software reset which will reset all register data bits to logic 0. to perform a software reset, bit d7 in the reset register is written with a logic 1. after the reset is complete, bit d7 is automatically set back to zero. table 4. serial programming mode register map (par/ ser = gnd) register a0: reset register (address 00h) write only d7 d6 d5 d4 d3 d2 d1 d0 reset x x x x x x x bit 7 reset software reset bit 0 = not used 1 = software reset. all mode control registers are reset to 00h. the adc is momentarily placed in sleep mode. this bit is automatically set back to zero at the end of the spi write command. the reset register is write only. data read back from the reset register will be random. bits 6-0 unused, dont care bits. register a1: format and power-down register (address 01h with cs = gnd) d7 d6 d5 d4 d3 d2 d1 d0 dcsoff rand twoscomp sleep nap_4 nap_3 nap_2 nap_1 bit 7 dcsoff clock duty cycle stabilizer bit 0 = clock duty cycle stabilizer on 1 = clock duty cycle stabilizer off. this is not recommended. bit 6 rand data output randomizer mode control bit 0 = data output randomizer mode off 1 = data output randomizer mode on bit 5 twoscomp twos complement mode control bit 0 = offset binary data format 1 = twos complement data format bits 4-0 sleep: nap_x sleep/nap mode control bits 00000 = normal operation 0xxx1 = channel 1 in nap mode 0xx1x = channel 2 in nap mode 0x1xx = channel 3 in nap mode 01xxx = channel 4 in nap mode 1xxxx = sleep mode. channels 1, 2, 3 and 4 are disabled note: any combination of these channels can be placed in nap mode. ltm9012 20 9012f a pplica t ions i n f or m a t ion register a2: output mode register (address 02h) d7 d6 d5 d4 d3 d2 d1 d0 ilvds2 ilvds1 ilvds0 termon outoff outmode2 outmode1 outmode0 bits 7-5 ilvds2:ilvds0 lvds output current bits 000 = 3.5ma lvds output driver current 001 = 4.0ma lvds output driver current 010 = 4.5ma lvds output driver current 011 = not used 100 = 3.0ma lvds output driver current 101 = 2.5ma lvds output driver current 110 = 2.1ma lvds output driver current 111 = 1.75ma lvds output driver current bit 4 termon lvds internal termination bit 0 = internal termination off 1 = internal termination on. lvds output driver current is 2 the current set by ilvds2:ilvds0. internal termination should only be used with 1.75ma, 2.1ma or 2.5ma lvds output current modes. bit 3 outoff output disable bit 0 = digital outputs are enabled. 1 = digital outputs are disabled. bits 2-0 outmode2:outmode0 digital output mode control bits 000 = 2-lanes, 16-bit serialization 001 = 2-lanes, 14-bit serialization 010 = 2-lanes, 12-bit serialization 011 = not used 100 = not used 101 = 1-lane, 14-bit serialization 110 = 1-lane, 12-bit serialization 111 = 1-lane, 16-bit serialization register a3: test pattern msb register (address 03h) d7 d6 d5 d4 d3 d2 d1 d0 outtest x tp13 tp12 tp11 tp10 tp9 tp8 bit 7 outtest digital output test pattern control bit 0 = digital output test pattern off 1 = digital output test pattern on bit 6 unused, dont care bit. bit 5-0 tp13:tp8 test pattern data bits (msb) tp13:tp8 set the test pattern for data bit 13(msb) through data bit 8. register a4: test pattern lsb register (address 04h) d7 d6 d5 d4 d3 d2 d1 d0 tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 bit 7-0 tp7:tp0 test pattern data bits (lsb) tp7:tp0 set the test pattern for data bit 7 through data bit 0(lsb). ltm9012 21 9012f a pplica t ions i n f or m a t ion g rounding and b ypassing the ltm9012 requires a printed cir cuit board with a clean unbroken ground plane. a multilayer board with an internal ground plane in the first layer beneath the adc is recommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. bypass capacitors are integrated inside the package; ad- ditional capacitance is optional. the analog inputs, encode signals, and digital outputs should not be routed next to each other. ground fill and grounded vias should be used as barriers to isolate these signals from each other. l a yout r ecommenda tions the pin assignments of the ltm9012 allow a flow-through layout that makes it possible to use multiple parts in a small area when a large number of adc channels are required. the l tm9012 has similar layout rules to other bga packages. the layout can be implemented with 6mil blind vias and 5mil traces. the pinout has been designed to minimize the space required to route the analog and digital traces. the analog and digital traces can essentially be routed within the width of the package. this allows multiple packages to be located close together for high channel count applications. trace lengths for the analog inputs and digital outputs should be matched as well as possible. table 5 lists the trace lengths for the analog inputs and digital outputs inside the package from the die pad to the package pad. these should be added to the pcb trace lengths for best matching. figures 7 through figure 11 show an example of a good pcb layout. h ea t t ransfer most of the heat generated by the ltm9012 is transferred from the die through the bottom side of the package through numerous ground pins onto the printed cir cuit board. for good electrical and thermal performance, these pins should be connected to the internal ground planes by an array of vias. table 5. internal trace lengths pin name (mm) q9 01a C 0.535 q10 01a + 0.350 r11 01b C 2.185 r12 01b + 2.216 r9 02a C 0.174 r10 02a + 0.667 s11 02b C 2.976 s12 02b + 2.972 s2 03a C 3.033 s3 03a + 3.031 r4 03b C 0.752 r5 03b + 0.370 r2 04a C 2.130 r3 04a + 2.125 q4 04b C 0.332 q5 04b + 0.527 a12 ch1 C 7.741 a11 ch1 + 7.723 a9 ch2 C 4.632 a8 ch2 + 4.629 a6 ch3 C 3.987 a5 ch3 + 3.988 a3 ch4 C 7.892 a2 ch4 + 7.896 p1 clk C 3.317 n1 clk + 3.325 p4 cs 0.241 s9 dco C 1.912 s10 dco + 1.927 s4 fr C 2.097 s5 fr + 2.082 p10 par/ ser 0.226 p5 sck 1.553 p9 sd0 0.957 p3 sdi 1.184 ltm9012 22 9012f a pplica t ions i n f or m a t ion figure 7. layer 1 component side ltm9012 23 9012f a pplica t ions i n f or m a t ion figure 8. layer 2 ltm9012 24 9012f a pplica t ions i n f or m a t ion figure 9. layer 3 ltm9012 25 9012f figure 10. back side a pplica t ions i n f or m a t ion ltm9012 26 9012f typical a pplica t ion ltm9012 9012 f11 ch1 + ch1 ? ch2 + ch2 ? ch3 + ch3 ? ch4 + ch4 ? in1 + in1 ? in2 + in2 ? in3 + in3 ? in4 + in4 ? ognd ognd ognd out1a+ out1a? out2a+ out2a? out3a+ out3a? out4a+ out4a? out1b+ out1b? out2b+ out2b? out3b+ out3b? out4b+ out4b? dco+ dco? fr+ fr? shdn1 shdn2 shdn3 shdn4 clk + clk ? gnd* v cc1 v cc1 v cc2 v cc2 v cc3 v cc3 v cc4 v cc4 par/ ser cs sck sdo sdi v ref sense ov dd ov dd ov dd v dd v dd v dd v dd c23 0.1f c24 0.1f c25 0.1f c8 1f c27 0.1f c26 0.1f c9 1f v dd r4 1k c7 2.2f tp3 1 3 2 j4 v dd v cc r10 1k c20 opt c31 0.01f c28 opt c32 opt r26 opt r20 49.9 r19 49.9 r25 opt r22 0 r16 0 t1 maba-007159-000000 l4 opt c29 c22 r24 opt ? ? j8 clk ? j6 1 3 2 j14 v dd v dd r64 1k r12 opt r15 opt r17 opt r21 opt r23 opt 1 3 2 j13 v dd r63 1k 1 3 2 j12 v dd r62 1k 1 3 2 j11 v dd r61 1k 1 3 2 j2 v dd r6 1k 1 3 2 j1 1 3 2 j5 opt v dd v cc r11 1k r70 0 l3 bead 1 3 2 j3 v dd r5 1k r3 31.6k r1 10k r2 1k v dd 3.3v out sen/adj in shdn byp gnd r7 2k c12 1f r9 1k c13 1f c33, 0.01f c35, 0.01f c37, 0.01f c39, 0.01f c34, 0.01f c36, 0.01f c38, 0.01f c40, 0.01f c6 1f c11 1f c10 4.7f c14 100f + r8 100 ov dd1 v dd1 r71 0 l2 bead out sen/adj in tp1 v + 3v to 6v tp4 5v to 6v tp2 gnd tp5 gnd shdn byp gnd lt1763-1.8 lt1763 c3 1f c4 1f c2 1f c1 4.7f c5 100f + r72 0 ov dd v dd l1 bead r29, 0 r30, 0 r31, 0 r32, 0 r33, 0 r34, 0 r35, 0 r36, 0 v dd1 ov dd1 c21 0.01f c30 0.01f r18 0 r13 opt r60 dns r14 opt r69 0 * other gnd pins omitted for clarity. figure 11. simplified schematic for example layout ltm9012 27 9012f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion bga package 221-lead (15mm 11.25mm 2.82mm) (reference ltc dwg # 05-08-1886 rev ?) s r q p n m l k j h g f e d c b a 123456 13 12 11 10 9 8 7 package top view 4 pin ?a1? corner y x aaa z aaa z detail a package bottom view 3 see notes pin 1 bga package 221-lead (15mm 11.25mm 2.82mm) (reference ltc dwg# 05-08-1886 rev ?) bga 221 0710 rev ? tray pin 1 bevel package in tray loading orientation component pin ?a1? notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature detail a ?b (221 places) detail b substrate a a1 b1 ccc z detail b package side view mold cap z m x yzddd m zeee symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 2.67 0.35 2.32 0.45 0.45 0.37 1.95 nom 2.82 0.40 2.42 0.50 0.50 15.0 11.25 0.80 12.80 9.60 0.42 2.00 max 2.97 0.45 2.52 0.55 0.55 0.47 2.05 0.15 0.10 0.12 0.15 0.08 notes dimensions total number of balls: 221 a2 d e e e b f g suggested pcb layout top view 0.00 3.20 3.20 6.40 4.00 4.00 4.80 4.80 5.60 5.60 6.40 0.80 0.80 1.60 1.60 2.40 2.40 4.80 2.40 1.60 3.20 4.00 2.40 1.60 0.80 0.80 4.80 4.00 3.20 0.00 5.35 5.85 ltmxxxxxx module // bbb z z h2 h1 b 5. primary datum -z- is seating plane 6. solder ball composition can be 96.5% sn/3.0% ag/0.5% cu or sn pb eutectic 0.50 0.025 ? 221x 4.25 3.75 please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. ltm9012 28 9012f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2012 lt 0412 ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments ltc2170-14/ltc2171-14/ ltc2172-14 14-bit, 25msps/40msps/65msps 1.8v quad adcs, ultralow power 178mw/234mw/360mw, 73.4db snr, 85db sfdr, serial lvds outputs, 7mm 8mm qfn-52 ltc2173-14/ltc2174-14/ ltc2175-14 14-bit, 80msps/105msps/125msps 1.8v quad adcs, ultralow power 376mw/450mw/558mw, 73.4 db snr, 88db sfdr, serial lvds outputs, 7mm 8mm qfn-52 LTC2263-14/ltc2264-14/ ltc2265-14 14-bit, 25msps/40msps/65msps 1.8v dual adcs, ultralow power 99mw/126mw/191mw, 73.4db snr, 85db sfdr, serial lvds outputs, 6mm 6mm qfn-40 ltc2266-14/ltc2267-14/ ltc2268-14 14-bit, 80msps/105msps/125msps 1.8v dual adcs, ultralow power 216mw/250mw/293mw, 73.4db snr, 85db sfdr, serial lvds outputs, 6mm 6mm qfn-40 ltm9009-14/ltm9010-14/ ltm9011-14 14-bit, 80msps/105msps/125msps 1.8v octal adcs, ultralow power 752mw/900mw/1116mw, 73.1db snr, 88db sfdr, serial lvds outputs, 11.25mm 9mm bga-140 ltm9012 9012 ta02 0.1f +in ?in 0v to 3v pulse signal 1.5v reference 3v ch1 + ch1 ? ? ? ? shdn1 shdn2 shdn3 shdn4 par/ ser v ref outa + outa ? ? ? ? sdo fr? fr + dco ? dco + 1k 1% ? + 464 1% 464 1% ? ltc6254 cs sck sdi enc + enc ? gnd v cc1 v cc2 v cc3 v cc4 v dd ov dd sense 3.3v 1.8v single-ended drive with unity gain example |
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